Differential Voltage Current Conveyor Research Articles

Integrable emulation of a floating incremental/decremental inverse memristor for memristor bandwidth extension

Abstract The article explores the compact emulation of the inverse memristor through a circuit-based approach. It introduces a floating emulator architecture that incorporates a dual output OTA (Operation Transconductance Amplifier) and DVCC (Differential Voltage Current Conveyor), along with two grounded passive elements, to achieve the emulation of an inverse memristor. The utilization of grounded resistance allows for tunability over the realized behaviour. A key contribution of this research is the novel application of the inverse memristor to extend the operating frequency range of any memristor emulator circuit. Validation of the proposed emulator circuit, in both incremental and decremental modes, along with its application, is conducted using PSPICE-generated simulation results in the 0.18 µm TSMC CMOS technology. Additionally, an inverse memristor emulator configuration employing the IC LM13700 is presented, and its functionality is tested through a breadboard implementation.

Realization of a memcapacitance emulator utilizing a singular current-mode active block

Abstract This paper introduces a novel circuit design for a memcapacitance emulator, employing a single Voltage Differencing Current Conveyor (VDCC) as its core element. The emulator circuit has been intricately designed, employing only capacitors as grounded passive components. One remarkable aspect of these circuits is their inherent electronic tunability, allowing for precise control of the achieved inverse memcapacitance. The theoretical analysis of the emulator includes a comprehensive examination of potential non-idealities and parasitic influences. Careful selection of passive circuit elements has been made to minimize the impact of these undesirable effects. In contrast to extant designs cataloged in the existing literature, the presented circuitry manifests remarkable simplicity in its configuration. Furthermore, it exhibits a wide operational frequency range, extending up to 50MHz, and effectively clears the non-volatility criterion. To substantiate the efficacy of the devised circuits, comprehensive LTSpice simulations have been conducted, employing a 0.18 μm TSMC process parameter and a power supply of ±0.9 V. These simulations provide robust evidence of the emulator’s performance, reaffirming the feasibility and practicality of the proposed approach in the domain of memcapacitance emulation.

Resistorless Floating/Grounded Memristor Emulator Model With Electronic Tunability

The realization of memristor devices with specific operating parameters is a challenging task, which drives innovation in emulation circuits. This article offers a simple and novel resistorless memristor emulator design with an electronic controllability feature. The proposed model is suitable for both floating and grounded memristor applications and can operate in incremental/decremental modes effectively without switches. The proposed model comprises a voltage differencing current conveyor (VDCC) and an operational transconductance amplifier (OTA) as active components and requires a single capacitor as its passive element. This model emulates the memristors pinched hysteresis loop in current-voltage (I-V) plane. Simulation is carried out for a 180 nm CMOS technology with a supply voltage of 10.9 V. The proposed design exhibits non-linear behavior for a wide range of input voltage and operates well up to 8 MHz. The reliability and robustness of the proposed design have been verified for short-term non-volatility, temperature variation, Monte-Carlo and process corner analysis. The experimental verifications are carried out on a breadboard using ICs AD844 and CA3080.

Design of a Fractional Order Low-pass Filter Using a Differential Voltage Current Conveyor

In this paper, an active implementation of a differential voltage current conveyor (DVCC) based on a low-pass filter operating in the fractional order domain is presented. The transfer function for a fractional order system is dependent on the rational approximation of sα. Different methods used for calculating the rational approximation, including Carlson, Elkhazalil, and curve fitting, are evaluated here. Finally, to validate the theoretical results, a fractional order Butterworth filter is simulated in the Pspice environment using the 0.5 micrometer CMOS technology with an R-C network-based fractional order capacitor. Additionally, using the Monte Carlo analysis, the impact of current and voltage faults on DVCC response is investigated. It has been inferred that realization with a wider bandwidth is possible.

A comparative study on the Implementation of Fractional Order Butterworth Lowpass Filter using Differential Voltage Current Conveyor

In this paper, two fractance devices and an active implementation of a differential voltage current conveyor (DVCC) based on a Butterworth lowpass filter in fractional order are presented (FDs). The transfer function for a frac- tional order system is initially established. The conventional fractional order Butterworth equa- tion is then used to compare the transfer func- tion of the created system. This can be equated to obtain the generalised condition under which the created system functions as a Butterworth fil- ter of fractional order. Additionally, using Monte Carlo analysis, the impact of current and voltage faults on DVCC response is investigated. Finally, to validate the theoretical results, a fractional or- der Butterworth filter is simulated in the PSpice environment using 0.5 μm CMOS technology us- ing a suggested R-C network-based fractional or- der capacitor.

Electronically Tunable Memristor Emulator Implemented Using a Single Active Element and Its Application in Adaptive Learning.

In recent times, much-coveted memristor emulators have found their use in a variety of applications such as neuromorphic computing, analog computations, signal processing, etc. Thus, a 100 MHz flux-controlled memristor emulator is proposed in this research brief. The proposed memristor emulator is designed using a single differential voltage current conveyor (DVCC), three PMOS transistors, and one capacitor. Among three PMOS transistors, two transistors are used to implement an active resistor, and one transistor is used as the multiplier required for the necessary memristive behaviors. Through simple adjustment of the switch, the proposed emulator can be operated in incremental as well as decremental configurations. The simulations are performed using a 180 nm technology node to validate the proposed design and are experimentally verified using AD844AN and CD4007 ICs. The memristor states of the proposed emulator are perfectly retained even in the absence of external stimuli, thereby ascertaining the non-volatility behavior. The robustness of the design is further analyzed using the PVT and Monte Carlo simulations, which suggest that the circuit operation is not hindered by the mismatch and process variations. A simple neuromorphic adaptive learning circuit based on the proposed memristor is also designed as an application.

Mixed-mode Multiphase Sinusoidal Oscillators using Differential Voltage Current Conveyor Transconductance Amplifiers and Only Grounded Passives Components

This article is about mixed-mode multiphase sinusoidal oscillators that are made up of differential voltage current conveyor transconductance amplifier (DVCCTA) and use all the grounded passive components. The proposed multiphase sinusoidal oscillators provide a single DVCCTA, a single grounded resistor and a capacitor for each phase which is suitable for integrated circuit implementation. In addition, the sinusoidal outputs generate currents and voltages simultaneously. The current signals from the outputs have high impedances, which make it easier to connect them directly to the next circuit or stage. The proposed circuits can generate multiphase sinusoidal signals that are both equally phased and in amplitude. The oscillation can be adjusted simultaneously of the frequency of oscillation by the electronic method. A simulation with the PSPICE program and an experiment with commercially available ICs (AD830, AD844, and LM13700N) demonstrated. The results show the efficiency of the circuit is completely consistent with the theory.

Design and Implementation of a Sense Amplifier for Low-Power Cardiac Pacemaker

This paper presents the implementation of a sense amplifier for a low-power cardiac pacemaker using the Differential Voltage Current Conveyor (DVCC). Two significant aspects of the pacemaker are sensing and pacing. The pulse generator, which is the heart of the pacemaker, consists of a sense amplifier, a logic unit and a timing control unit. The sense amplifier comprises an instrumentation amplifier, a bandpass filter and a comparator that are used to detect the QRS complex wave from the cardiac signal. Based on the output of a sense amplifier, the logic unit and the timing control unit decide whether to pace the heart or not, which achieves the requirement of the demand pacing. In this paper, a novel design of the sense amplifier using a DVCC is proposed, and the simulations are performed using 130-nm TSMC technology. Furthermore, the modes of the pacemaker VVI, DDD and rate-responsive algorithms have been implemented using the structural approach in VHDL by taking into consideration the timing cycles of a pacemaker. The design analysis shows that the proposed model of pacemaker is highly efficient and consumes significantly less energy.

Two New Voltage-Mode Sinusoidal Quadrature Oscillators Employing Second-Generation Voltage Conveyors

This article presents an application of a second-generation voltage conveyor (VCII) as a quadrature oscillator. The controlling parameters of the presented circuits, i.e. oscillation condition and oscillation frequency are tuneable without affecting the other. Both the single-resistance-controlled oscillators employ only two VCII, two grounded capacitors, and three grounded/ virtually grounded resistors. To strengthen the design idea regular mathematical analysis such as ideal, non-ideal, parasitic, frequency stability, phase noise analysis, and sensitivity calculations have been performed. To validate the proposed networks, the simulations have been carried out using 180 nm CMOS technology parameters, and experimental studies have also been performed using commercially available integrated circuits. Abbreviations: VDTA: voltage differencing transconductance amplifier; CDBA: current differencing buffered amplifier; OTRA: operational transconductance amplifier; CCI: first generation current conveyor; CCII: second generation current conveyor; ICCII: Inverting current conveyor; CFOA: current feedback operational amplifier; CDTA: current differencing transconductance amplifier; VDDDA: voltage differencing differential difference amplifier; OTA: operational transconductance amplifier; DVCC: differential voltage current conveyor; DXCCTA: dual:X current conveyor transconductance amplifier; M: MOS model; H: Hardware experimentation; BJT:Bipolar Junction Transistor; MM: Macro-model Simulation.

Electronically Adjustable Multiphase Sinusoidal Oscillator with High-Output Impedance at Output Current Nodes Using VDCCs

This paper presents the high-output-impedance current-mode multiphase sinusoidal oscillators (MSO) using voltage differencing current conveyor (VDCC)-based lossy integrators, which consist of one VDCC, one grounded capacitor, and two grounded resistors. The proposed oscillator can provide an odd-phase and even-phase system without the use of an additional amplifier. The frequency of oscillation (FO) is electronically tuned via the bias current without affecting the condition of oscillation (CO). The proposed oscillator is designed to obtain three-phase sinusoidal waveforms (n = 3). The effect of non-idealities of VDCC on the lossy integrator section is also investigated. The validity of the proposed circuit is demonstrated by PSPICE simulation using 0.18 µm TSMC CMOS process parameters with ±0.9V power supply. The frequency of oscillation obtained from the simulation is 1.43 MHz. The total harmonic distortions of the sinusoidal output currents IO1, IO2, and IO2 are 1.22%, 1.18%, and 0.57%. The IO1–IO2 and IO2–IO3 phase differences are approximately 121 and 119 degrees, respectively. The feasibility of the proposed MSO is also verified with experimental results using the VDCC constructed from the commercially available ICs (LT1288 and AD844) with ±5 V power supply. The results of PSPICE simulations and experiments are closely consistent with the theoretical expectation.

A compact floating and grounded memristor model using single active element

Memristor with defined operational specifications is a challenging task that promotes innovation in emulation circuit modelling. This article presents a single active block based compact memristor emulator architecture which is suitable for both floating and grounded circuit topologies. It effectively operates in incremental/decremental modes in both the configurations. The proposed model utilizes only one Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) as an active block along with a few passive components. It discourages the use of extra sub-circuit components like multiple active blocks, summers and multipliers. The circuit is intended to work at ±1 V of dc power supply and has a power consumption of 8.74 mW. The proposed emulator model exhibits all the characteristics of an ideal memristor with an operating frequency of 12.8 MHz. It has wide working voltage range of 50–500 mV. The memristor model is built and simulated using the TSMC 0.18 μm CMOS process parameter. The reliability and effectiveness of the proposed model is verified through non-ideal, Monte-Carlo, process corner, non-volatility and temperature variation analysis. Furthermore, the memristor prototype is constructed on the breadboard using discrete ICs AD844AN and CA3080. The experimental outcome is found in accordance with the simulation. The applicability of the proposed memristor model is verified by implementing a memristor based Schmitt trigger circuit.

Synthetic Transformer using Operational Transconductance Amplifier (OTA) and Voltage Differencing Current Conveyor (VDCC)

This paper presents a new realization of synthetic transformer using off the shelf active blocks. This proposed transformer is designed using operational transconductance amplifier (OTA), voltage differencing current conveyor (VDCC), resistor and capacitor. Use of VDCC helps to utilizes benefits of both voltage differencing unit and current conveyor. The working of proposed circuit is verified through simulations in LTSPICE using TSMC 180nm process characteristics. The proposed circuit offers the feature of adjusting primary and secondary self-inductances and mutual inductance independently. The bias current of the VDCC is used to control the primary and secondary self-inductance and mutual inductance of synthetic transformer.

Electronically Independent Gain Controllable Integrable Trans-Admittance Mode Universal Filter: An Application for Modern Radio Receiver

This paper represents a new integrable trans-admittance mode universal filter employing an active building block, i.e., Voltage Differencing Current Conveyor, and all grounded passive elements. The proposed circuit can easily realize all five, widely used, filter responses, i.e., bandpass, high pass, low pass, all pass and band-reject. The designed circuit configuration provides favorable impedances at the input as well as output ports. Independent tunability of its gain parameter and orthogonal tunability of its quality factor and operating frequency are some of the noteworthy features of the designed circuit. The simulations of the designed filter are verified by 180-nm Complementary Metal Oxide Semiconductor (CMOS) technology in the SPICE simulation environment. Validation of the proposed design is done by experimental work along with the regular mathematical analysis.

A Modern VDCCTA Active Element and Its Electronic Application

In this paper, a novel current mode (CM) building block termed Voltage differencing current conveyor transconductance amplifier (VDCCTA) is developed by combining the voltage differencing current conveyor (VDCC) and an operational transconductance amplifier (OTA). This modern active block VDCCTA is extended for applications such as a lossless inductor, filter design, and chaotic circuit design. An active inductor simulator (AIS) without any component matching is designed using the proposed VDCCTA block and a grounded capacitor as a first application that offers flexibility to model grounded positive active inductor (GPAI), grounded negative active inductor (GNAI), and floating positive active inductor (FPAI) circuits. Moreover, the proposed positive active inductor (PAI) can also be translated for multiple input single output (MISO) voltage mode (VM) universal filter with two external passive elements and chaotic circuitry. The characteristics of VDCCTA are verified with the CM multifunction filter, VM band-pass filter, and VM-MISO filter. A complete exercise of this newly reported VDCCTA block is analyzed for their port characteristics validation and the performance parameters using PSPICE simulation. Finally, experimental verification of the proposed AIS is tested to justify the theoretical and simulated results.

Compact tunable memristor and inverse-memristor emulators with grounded passive elements

ABSTRACT The circuit-based emulation of memristor elements is becoming increasingly popular due to various advantages it offers over the physical architectures. The work reported in this paper presents the architectures of two novel circuit configurations dedicated to the realisation of an ideal memristor and a new but useful element, inverse memristor, respectively. Both presented circuit emulators are based on VDCC (Voltage Differencing Current Conveyor) active element. Over the previously reported bulky circuit emulators, the presented emulators have a significant design-related advantage since these are multiplier-less and grounded elements-based architectures. The developed circuits possess a tunability feature with respect to biasing voltage as well as the employed resistance. The mathematical description of pinch-off tuning and utilisation of inverse-memristor (for achieving better control over memristor characteristics) have been discussed with MATLAB simulations. To verify the workability of presented circuit architectures, the PSPICE environment has been chosen for simulation purpose. All the simulation results have been illustrated and discussed in detail. Later, the presented emulator circuits are developed using commercial ICs like CA3080 and AD844, and related results are described.

Four Unity/Variable Gain First-Order Cascaded Voltage-Mode All-Pass Filters and Their Fully Uncoupled Quadrature Sinusoidal Oscillator Applications.

This paper presents four new designs for a first-order voltage-mode (VM) all-pass filter (APF) circuit based on two single-output positive differential voltage current conveyors (DVCCs). The first two proposed VMAPFs with unity-gain, high-input (HI) impedance and low-output (LO) impedance use two DVCCs, a grounded capacitor, and a grounded resistor. The last two proposed first-order VMAPFs with HI impedance and variable-gain control are two resistors added to each of the first two VMAPFs. The last two proposed first-order VMAPFs with variable-gain control use two DVCCs, one grounded capacitor, and three grounded resistors and provide HI impedances, so that VMAPFs can be directly cascaded to obtain high-order filters without additional voltage buffers. The four implementation circuits based only on grounded passive components are particularly applicable for integrated circuits (ICs). To confirm the cascading characteristics, an application example of a fully-uncoupled quadrature sinusoidal oscillator (FQSO) is also proposed. PSpice simulation results have confirmed the feasibility of the proposed structures. VMAPF and FQSO circuits are also constructed from commercial AD8130 and AD844 ICs, and their experimentally measured time and frequency responses are compared to theoretical values. The supply voltages for both the AD8130 and AD844 ICs were ±5 V. The measured power dissipation of the proposed first-order VMAPF and second-order FQSO circuits is 0.6 W. The measured input 1-dB compression point for the four VMAPFs is about 19 dB. The measured total harmonic distortion of the four VMAPFs is less than 0.67% when the input voltage reaches 2.5 Vpp. The calculated figures of merit for the four VMAPFs are 628.2 × 103, 603.06 × 103, 516.53 × 103, and 496.42 × 103, respectively.

Electronically Tunable Mixed Mode Universal Filter Employing Grounded Passive Components

A recently developed active element, namely Voltage Differencing Differential Voltage Current Conveyor (VD-DVCC), is employed in the design of electronically tunable mixed-mode universal filter. The filter provides low pass (LP), high pass (HP), band pass (BP), band reject (BR) and all pass (AP) responses in voltage-mode (VM), current-mode, trans-impedance-mode (TIM) and trans-admittance-mode (TAM). The filter employs two VD-DVCCs, three resistors and two capacitors. All the passive components employed are grounded. The attractive features of the filters include: (i) ability to operate in all four modes, (ii) use of grounded passive components, (iii) tunability of Q factor independent of pole frequency, (iv) high input impedance for VM and TIM mode, (v) high output impedance explicit current output for CM and TAM and (vi) no requirement for double/negative input signals (voltage/current) for response realization. The VD-DVCC is designed and validated in Cadence virtuoso using 0.18µm PDK at supply voltage of ±1V. The operation of filter is examined at 5.305 MHz frequency. The non-ideal gain and sensitivity analysis is also carried out to study the effect of process and components spread on the filter performance. The obtained results bear close resemblance with the theoretical findings.

New single VDCC Based Electronically Adjustable FDNR using Grounded Capacitances

A FDNR (Frequency Dependent Negative Resistance) simulator has been presented, which uses single Voltage Differencing Current Conveyor (VDCC) along with two grounded capacitances to realize the pure FDNR function. The proposed FDNR simulator places itself as one of the most compact circuit architecture present in the available literature. It is a resistor-less realization and finds no requirement of any active/passive component/parameter matching to realize the FDNR behaviour. The presented analysis shows that the proposed circuit remains always stable under the effect of parasitics irrespective of any values of circuit parameters, which is not witnessed in many previously reported FDNRs. The usability of realized synthetic FDNR has been checked through validation of developed higher-order CDR filters by using the proposed FDNR. To verify the designed circuits, the presented configurations have been simulated under the PSPICE simulation environment. The experimental results are shown for the commercial ICs (AD844 and CA3080) based physical realization of described FDNR.

DVCC Based (2 + α) Order Low Pass Bessel Filter Using Optimization Techniques

This paper proposes the design and analysis of (2 + α) order low pass Bessel filter using different optimization techniques. The coefficients of the proposed filter are obtained by minimizing the error between transfer functions of (2 + α) order low pass filter and third-order Bessel approximation using simulated annealing (SA), interior search algorithm (ISA), and nonlinear least square (NLS) optimization techniques. The best optimization technique based on the error in gain, cut-off frequency, roll-off, passband, stopband, and phase is chosen for designing the proposed filter. The stability analysis of the proposed filter has also been done in W-plane. The simulated responses of the best optimized proposed filter are attained using the FOMCON toolbox of MATLAB and SPICE. The circuit realization of 2.5 order low pass Bessel filter is done using two DVCCs (differential voltage current conveyors), one generalized impedance converter (GIC) based inductor, and one fractional capacitor. The proposed filter is implemented for the cut-off frequency of 10 kHz using a wideband fractional capacitor. Monte Carlo and noise analyses are also performed for the proposed filter. The MATLAB and SPICE results are shown in good agreement.

A Band-Pass Instrumentation Amplifier Based on a Differential Voltage Current Conveyor for Biomedical Signal Recording Applications

Recently, due to their abundant benefits, current-mode instrumentation amplifiers have received considerable attention in medical instrumentation and read-out circuit for biosensors. This paper is focused on the design of current-mode instrumentation amplifiers for portable, implantable, and wearable electrocardiography and electroencephalography applications. To this end, a CMOS differential voltage second-generation current conveyor (DVCCII) based on a linear transconductor is presented. A new band-pass instrumentation amplifier, based on the designed DVCCII, is also implemented in this paper. The concept of the proposed differential voltage current conveyor and instrumentation amplifier is validated numerically and their predicted performance is presented. The simulation results of the presented circuits were tested for 0.18 μm TSMC CMOS technology in a post layout simulation level using the Cadence Virtuoso tool with a ±0.9 V power supply, and demonstrated that the designed DVCCII has a wide dynamic range of ±400 mV and ±0.85 mA and a power consumption of 148 μW. The layout of the DVCCII circuit occupies a total area of 0.378 μm2. It is shown that the designed DVCCII benefits from good linearity over a wide range of input signals and provides a low input impedance at terminal X. Two versions of the proposed band-pass instrumentation amplifier using pseudo resistances were designed with different specifications for two different applications, namely for EEG and ECG signals. Numerical analyses of both designs show proper outputs and frequency responses by eliminating the undesired artifact and DC component of the EEG and ECG input signals.